Applicants claim the foreign priority benefits under 35 U.S.C. 119 of Japanese Application No. 6-221614 filed in Japan on Sep. 16, 1994. This Japanese Application and its translation are incorporated by reference into this Application.
This invention pertains to cache memories and, more particularly, to a means for preserving cache consistency when a CPU accesses a plurality of physical memories having different memory architectures.
Computer systems have recently emerged which enable operation in a mode different from a standard operation mode. In such a system, the CPU switches the system operation from the standard mode to the special mode. The special mode is mainly used to reduce power consumption in a personal computer. A block diagram of a computer system is shown in FIG. 5. This system is employed in small computer systems such as personal computers, and comprises a CPU, a cache, a memory, and a memory controller. The difference from the standard personal computer system lies in that the memory is physically divided into a standard memory and a system management memory or "SMRAM".
The CPU employing the special mode as described above switches its operation mode from the standard mode to the special mode when it receives a system management interrupt. Such a switched special mode is called the system management mode ("SMM").
When the CPU operates in the system management mode, it uses a special physical memory architecture called SMRAM which differs from the memory architecture used in the standard mode. This memory stores SMM handler codes, system-specific SMM data, and information representing the status of the CPU.
Referring to FIG. 1, the CPU 1 uses the standard memory 10 in the standard mode. However, for a certain address range (for example, 30000-3FFFF) the SMRAM 12 used in the system management mode is mapped in an overlapped fashion. In this specification, this physical address region is called an SMM region 3 herein to distinguish from other non-SMM regions 5.
When the CPU switches the system operation mode from the standard mode to the system management mode, it holds an SMIACT# line low. This causes the memory controller 16 to switch to the system management mode in order to switch from the standard memory to the SMRAM. The SMIACT# line is shown, for example, in FIG. 4. The CPU then stores the current register status information from the first address of the SMRAM in a manner similar to a stack. This is called a status save. When the status save processing is completed, the SMI handler starts execution.
A cache 14 is situated between the memory controller and the CPU to increase access speed. The cache 14 covers such overlapped and mapped SMM regions also, as with other regions. Therefore, when the SMM region is accessed, the cache has two possible statuses, one containing data related to the standard mode stored from the standard memory, and the other containing data related to the system management mode stored from the SMRAM.
Because the possibility exists that the cache 14 has data stored from two types of memory on a cache line related to the same physical address, there may arise a problem when the CPU accesses the cache memory after when it switches mode, for example, from the standard mode to the system management mode. In this case, if a cache line related to the physical address requested by the CPU exists in the cache, a cache hit occurs and the data is sent to the main memory. However, the data stored in the cache is that stored from the standard memory, which differs from the data stored from the SMRAM related to the same physical address requested by the CPU. Therefore, if the data is sent to the main memory based on only the fact that the cache has received a cache hit, the data actually requested by the CPU fails to match the data being sent.
In other words, this problem has been caused by the fact that the data in the cache memory is not always read from the SMRAM. Such a problem is called a cache inconsistency.
In a system employing a method to perform an operation with different physical memory whenever the mode is switched, many attempts have been taken to prevent such cache inconsistencies. One of these methods is to flush the cache each time the CPU switches its mode. According to this method, because all data stored in the cache is erased each time the operation mode is changed, the above-mentioned cache inconsistency problem does not arise. The cache flush itself, however, has the following problems:
First, the cache flush equally erases all data in the cache. That is, even valid (consistent) data present in the cache becomes subject to being flushed. This is an ineffective operation. Furthermore, data must be restored to the cache from a "cold start" where the contents of the cache is built from scratch, which requires considerable time.
Second, the time taken by the cache flush itself becomes a problem. This cache flush operation returns cache data by checking all cache lines for whether or not there is data on each cache line. Performing such an operation consumes a considerable amount of time similar to filling the cache from the cold start described above.
Cache sizes have continued to increase, a trend which directly affects in the time required for the cache flush itself. It can therefore be understood that the conventional method of flushing the cache each time the CPU switches modes is becoming impractical.